1. Field of the Invention
This invention relates to a frequency divider of pulses using ring-counters and, more particularly, to a frequency divider suited for being used in a clock generator for solid-state imaging devices.
2. Description of the Related Art
The solid-state imaging devices such as Charge-Coupled Devices (CCD's) are constructed to a matrix of imaging elements, vertical shift registers disposed along each column of the imaging element matrix, a horizontal shift register receiving charges generated in the imaging elements through the vertical shift registers, and a charge-voltage converter producing an image signal in accordance with charges transferred from the horizontal shift register. The horizontal shift register is driven with horizontal clock pulses .phi..sub.HfCK having a repetition frequency larger than the color sub-carrier frequency f.sub.sc (i.e. 3.58 MHz in NTSC system). The repetition frequency of the horizontal clock pulses .phi..sub.HfCK is selected to be several integer times that of the color sub-carrier frequency f.sub.sc.
For generating such horizontal clock pulses .phi..sub.HfCK, a Phase-locked loop (PLL) is used. An output frequency of a voltage-controlled oscillator (VCO) is divided into a half to obtain the horizontal clock pulses .phi..sub.HfCK. The obtained frequency is divided into one-505th. The divided signal is compared with a fixed frequency with a phase detector. The VCO is controlled with the output from the phase detector through a low-pass filter.
The frequency division into one-505th was conventionally achieved by a combination of a one-fifth divider and a one-101st divider. The divider combination is formed of binary counters which operate with various frequencies to generate various frequency noises. The noises affect the image signal to produce synchronous noises or fixed pattern noises on a reproduced picture.